Dr. Nagendra Gulur
University of North Texas
Computer Science and Engineering
Email:

Education

PhD, Indian Institute of Science, 2015.
Major: Computer Engineering
Degree Specialization: Computer Architecture
Dissertation Title: Multi-Core Memory System Design: Developing and Using Analytical Models for Performance Evaluation and Enhancements

Professional Memberships

Individual Member, RISCV Foundation. (December 15, 2019 – Present).

Association for Computing Machinery. (January 01, 2015 – Present).

Awards and Honors

Senior Member Technical Staff, Texas Instruments. (February 2011 – Present).

Teaching

Teaching Experience

University of North Texas
CSCE 3600, Principles of Systems Programming, 1 course.
CSCE 4610, Computer Systems Architecture, 1 course.
CSCE 4890, Directed Study, 1 course.

Teaching at Other Institutions

University of Texas at Dallas, Advanced Digital Logic, EEDG/CE 6301, Spring 2019.

Non-Credit Instruction

Guest Lecture, 20. (November 4, 2019November 4, 2019).

Research

Published Intellectual Contributions

Conference Proceeding
Marathe, Y., Gulur, N., Ryoo, J. H., Song, S., John, L. K. (2017). CSALT: Context Switch Aware Large TLB. Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture. 449--462. New York, NY, USA: ACM. http://doi.acm.org/10.1145/3123939.3124549
Ryoo, J. H., Gulur, N., Song, S., John, L. K. (2017). Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB. Proceedings of the 44th Annual International Symposium on Computer Architecture. 469--480. New York, NY, USA: ACM. http://doi.acm.org/10.1145/3079856.3080210

Contracts, Grants and Sponsored Research

Grant - Research
Kavi, K. M. (Principal), Gulur, N. (Co-Principal), "EMPOWER: High-Performance, Low-Power and Fully Programmable Neural Network Architecture," Sponsored by Semiconductor Research Consortium (SRC), Other, $240000 Funded. (January 01, 2020December 31, 2022).

Copyrights, Patents

Patent
Gulur, N., John, L. K., Ryoo, J., "PROCESSOR USING A LEVEL 3 TRANSLATION LOOKASIDE BUFFER IMPLEMENTED IN OFF-CHIP OR DIE-STACKED DYNAMIC RANDOM ACCESS MEMORY," US 10,296,465. Regular, United States, Date Patent Approved: May 21, 2019 –.
Gulur, N., John, L. K., Marathe, Y., Ryoo, J., "INTELLIGENTLY PARTITIONING DATA CACHE TO ALLOCATE SPACE FOR TRANSLATION ENTRIES," US 10,261,915. Regular, United States, Date of Patent Application: September 15, 2017 –. Date Patent Approved: April 16, 2019 –.

Awards and Honors

ACM India Doctoral Dissertation Award, ACM India. (2017 – Present).

Service

University Service

Committee Member, Graduate Committee. (September 2019 – Present).

Host of Guest Artist, Distinguished Speaker Series. (December 4, 2019December 4, 2019).